This invention relates to a dividing circuit for dividing a dividend of a plurality of m-ary digits by a divisor of at least one m-ary digit, where m represents 2.sup.N, where N represents, in turn, a predetermined decimal integer which is not less than one. Each m-ary digit of the dividend and the divisor is therefore a binary, a quaternary, an octonary, a hexadecimal, or a like digit. More particularly, the dividing circuit is for calculating a quotient together with a residue. In connection with this invention, it should be noted that each of the dividend and the quotient can be said to consist of a plurality of m-ary digits without loss of generality.
Such a dividing circuit is useful in many fields of application, such as in an electronic digital computer. More specifically, the dividing circuit is a fixed-point dividing circuit according to this invention.
In the manner which will later be described with reference to one of a few drawing figures of the accompanying drawing, many machine cycles are necessary on calculating the quotient by a conventional dividing circuit. An improved dividing circuit is disclosed in U.S. Pat. No. 4,725,974 issued to Takashi Kanazawa. The improved dividing circuit is capable of achieving a high throughput. However, the improved dividing circuit comprises a great amount of hardware.